Electronic combination lock

ABSTRACT

Electronic combination lock circuitry responsive to either a primary or secondary code includes a plurality of logic gates adapted to be selectively connected with one of two pushbutton ordered sequences associated with the primary and secondary codes to control a multistage serial shift register which in turn selectively enables the logic gates in the ordered sequence and provides a lock/unlock criteria. The circuitry is normally programmed to respond to the primary code but may be rendered responsive to the secondary code by simultaneous actuation of two pushbuttons after the primary code has been entered.

United States Patent [191 Walters 1 ELECTRONIC COMBINATION LOCK [75] Inventor: William L. Walters, Santa Barbara,

Calif.

[73] Assignee: General Motors Corporation,

Detroit, Mich.

[22] Filedz Oct. 30, 1972 [21] App]. No.: 302,023

111 I 3,766,400 '14s] Oct.16,11973 3,641,396 2/1972 Kossen et a1 317/134 Primary Examiner-Robert K. Schaefer Assistant Examiner-William J. Smith AttorneyEugene W. Christen et al.

[57] ABSTRACT Electronic combination lock circuitry responsive to either a primary or secondary code includes a plurality of logic gates adapted to be selectively connected with one of two pushbutton ordered sequences associated with the primary and secondary codes to control a multistage serial shift register which in turn selectively enables the logic gates in the ordered sequence and provides a lock/unlock criteria. The circuitry is normally programmed to respond to the primary code but may be rendered responsive to the secondary code by simultaneous actuation of two pushbuttons after the primary code has been entered.

4 Claims, 2 Drawing Figures [52] US. Cl. 307/10 AT, 317/134, 340/64 [51] Int. Cl E051) 49/00 [58] Field of Search 317/134; 307/10 AT;

[56] References Cited UNITED STATES PATENTS 3,718,202 2/1973 Brock 180/114 3,710,316 1/1973 Kromer 307/10 AT X 3,660,729 5/1972 James et al. 317/134 KEYI POWER UP W KEYZ LOCKED TURNOVER PMENIEDncI 15 I973 SHEET 2 (If 2 LOCKED TURNOVER BIT 5 BIT 3 IGN LOCKED ELECTRONIC COMBINATION LOCK This invention relates to electronic combination locks and more particularly to motor vehicle anti-theft apparatus incorporating an electronic combination lock.

One of the major obstacles to the incorporation of electronic combination locks on automobiles has been the vehicle turnover situation. The necessity for transmitting the lock combination to each user is undesirable since a thief could obtain the combination on one occasion and use it to steal the vehicle on another occasion. A number of turnover options exist including the allowance of some limited total distance, total time or number of starts or limitations in gear ranges or speed.

A multitude of situations and conditions must be considered, however, when dealing with the problem of vehicle turnover. These include the situation where the vehicle is turned over to a parking lot attendant, whether it be valet parking covering potentially long distances such as at an airport, or parking by an attendant at a lot or restaurant where the keys are either maintained in the car to enable quick repositioning of the vehicles or where the keys are maintained on a rack. Furthermore, the loan of the vehicle could range from hours to days or the servicing of the vehicle could result in a need for numerous engine starts during say a tune-up or trouble analysis.

One turnover approach is disclosed in copending application Ser. No. 271,141, filed July 12, 1972 by John A. Weber and assigned to the assignee of the present invention. In that application a number of free starts, the exact quantity being determined by the operator, are provided assuming the vehicle has been started via the normal combination. That approach requires a speculative determination as to how many times the car will be started between the time the vehicle is turned over and when it is returned to the owner. This presents a problem for the attendant at parking lots where cars are stacked and are frequently moved to free other vehicles; and to service station personnel since the car will be started frequently to move it onto a rack, for road test and for evaluation of the repair.

In accordance with the present invention, electronic circuitry is provided which isresponsive to a primary combination code number and which may be programmed to respond to a secondary combination number orturnover'code once the primary code has been properly entered. By utilizing twoseparate codes the vehicle may be turned over to a'user without limitation as to the number of starts or other operating conditions, but without jeopardizing thesecurity 'or the system when placed in the primary mode upon return to theowner.-

Accordingly, it is a primary object of the present invention to provide an improved electronic combination-- lock normally responsive to only a primary combination code but which-may be rendered responsive to a tion includes a source of direct current potential which may be the vehicle battery and is designated by the numeral 10. The positive terminal of the battery 10, designated 8+ is connected through a polarity protection diode 12 to one side of a plurality of operator-actuable switch means shown as pushbuttons designated 81-85. The voltage of the battery 10 is regulated by a zener diode l4 and filtered by a capacitor 16. The other side of the switches 81-85 is connected to ground through pulldown resistors 20-28 respectively. The other side of the switches Sl-SS are also connected with priority logic generally designated 30. The lines designated KEY1KEY5 are driven high upon closure of the pushbutton switches Sl-S5 respectively and the logic 30 prevents simultaneous closure of any of the switches 81-85 from causing more than one of the outputs KEYl-KEYS from going high. Hereinafter, the terms high and low are used interchangeably with logic 1 and logic 0 respectively. The switch S1 is connected as one input to NOR gates 32 and 34 while the switch S2 is connected as another input to the gate 34 and through an inverter 35 to the other input of the gate 32. The switch S3 is connected as one input to a NAND gate 36 and through an inverter 38 to one input of a NAND gate 40. The other input to the gate 40 is the output of the gate 34. The switch S4 is connected as one input to a NOR gate 42 and through an inverter 44 to one input of a NOR gate 46. The switch S5 is connected to one input of the NAND gate 48, the other input of which is connected to the output of the gate 42. The output of the gates 36 and 48 are inverted by inverters 50 and 52 respectively. The pulldown resistors 20-28 normally hold KEYl through KEYS low in the absence of closure of any of the switches S1 through S5. Closure of any one of the switches 81-85 will drive the corresponding lines KEYl KEYS high. The priority logic 30 inhibits the lines KEY2 -KEY5 upon closure of the switch S1 and inhibits the lines KEY3 KEYS upon closure of the switch S2. Similarly, each lower priority line is inhibited by closure of the switches S3 and S4. Consequently, simultaneous closure of any of the switches S1S5 will cause only the highest priority (lowest KEY number) output to be driven high.

The outputs of the gates 42 and 48 provide inputs to a NAND gate 54, the output of which is connected with a shift register clock generator and digital filter generally designated 56, comprising D type flip-flops 58 and and NAND gate 62. The output of the gate 54 is connected to the data input, designated D, of the flipflop 58 and to the D input of the flip-flop 60 through the NAND gate 62. The other input to the NAND gate 62 is from the Q output of the fliprflop 58. The clockinputs, designated CL, of the flip-flops 58 and 60, are,

connected with an oscillator generally designated 64 comprising inverters 66 and 68, resistor 70 and capacitor 72. The oscillator 64 provides a periodic positive I going pulse of, for example, 25 cycles per second for secondary combination code subsequent to entry of the primary combination code.

Other objects and advantages of the present invention maybe had from the following detailed description which should be read in conjunction with the drawings in which g FIGS. 1 and Marc a schematic diagram of the electronic lockof the present invention.

Referring now to the drawings and initially to FIG. 1,

the electronic combination lock of the present invenclocking the flip-flops 58 and 60. Upon closure of any of the switches Sl-SS, one of the inputs to the gate 54 will be driven low causing its output to go high. On the following rising edge. of the output of the oscillator 64, the Q output of the flip-flop-58 is driven high causing the output of the gate 62 to go low. On the next rising edge of the output of the oscillator 64 the Q output of the flip-flop 60 goes low and the 0* output goes high. Unless the switch is held in for two cycles of the oscillator 64, STROBE will not be generated. This provides STROBE, is connected with the clock input, designated CL, of a five bit shift register generally designated 74.

The shift register 74 comprises five D type flip-flops 76-84, each having their Q outputs connected with the D inputs of the succeeding flip-flop. The reset input to each of the flip-flops 76-84 is connected to the output of a NAND gate 86. One input to the gate 86 designated lGN is connected to B+ through the vehicle ignition switch 88 and a filter network generally designated 90 comprising resistors 92 and capacitor 96. The other input to the gate 86 is designated POWER UP and is connected to B+ through a filter network generally designated 98 comprising resistor 100 and capacitor 104. When the ignition switch 88 is open, pulldown resistor 94 causes the IGN input to the gate 86 to go low causing its output to go high to reset the flip-flops 76-84 causing their respective Q outputs, designated BITS BIT1,.to go low. The outputs of the flip-flops 76-84are inverted by inverters 106-114 and provide the outputs designated BITS? BIT1*.

A mode select flip-flop generally designated 116 comprises NAND gates 118 and 120 having their inputs and outputs. interconnected. The output of the gate 118 is designated PRIMARY and the output of the gate 120 is designated TURNOVER. The flip-flop 116 is placed in the PRIMARY mode by simultaneous closure of the switches S1 and'S5 which cause the inputs to the NAND gate 122 to both go high and its output to go low to switch the output of the gate 118 high. A third input to the gate 118 is POWER UP. Consequently, if the battery is disconnected the capacitor 104 will be in a discharged state when power is reapplied due to resistor 102, and the system will be placed in the PRIMARY mode. The flip-flop 116 may be switched to the TURNOVER mode by driving the output of a NAND gate 124 low by simultaneous closure UNLOCKED is high. As will be explained hereinafter, if the system is-in the PRIMARY-mode the input designated UNLOCKED will. be high only after'the PRI- MARY code has been properly entered. The mode flipflop 116 controls select gates 126, 128 and l30 which determine'which of thetwoco des must" be entered. In

the example shown in the. schematic the PRIMARY codeof 21335 andtheTURNOVERcode of,l23 has been established. The select gates 126-130 each in clude a pair of AND gates designated by the subscripts,

PRIMARY mode the output of the gates 126,128 and 130 go high in response toclosure' of the pushbutton switches S2, S1 and S3 respectively, while in the TURNOVER nio'de'theoutput of the gates 126, 128 and 130 go'high in response to closure of the switches S1, S2 and S3 respectively. v

Sequence control means comprising NAND gates 132-140 are sequentially enabled anddisabled under the control of the register 74. The output of the gates '40 of the switches S2 and S4 whilexthe input designated- 132, 134 and 136 provide inputs to an OR function performing NAND gate 144 while the outputs of the gates 138 and 140 are ORed by a NAND gate 142 and inverted by an inverter 146 to provide a fourth input to the gate 144.

The gate 132 is enabled when the register 74 is reset upon opening of the ignition switch 88 by the BIT5* input while the gates 134-140 are disabled by the BITS-BITZ inputs respectively. If the lock is in its primary mode of operation and S2 is the first pushbutton actuated following closure of the ignition switch 88, the output of the gate 132 goes low and the output of the gate 144 goes high providing a logic 1 at the D input to the flip-flop 76 which will be transferred to its Q output on the rising edge of the clock pulse resulting from closure of the switch S2. Accordingly, BIT5* will go low disabling the gate 132 and BITS will go high enabling the gate 134. If S1 is now actuated all inputs to the gate 134 will be high driving its output low and the output of the gate 144 high. On the rising edge of a clock pulse resulting from actuation of S1 a logic I is transferred tothe Q output of the flip-flop 76 and the previous logic 1 input to the flip-flop 78 is transferred to its Q output causing BIT4 to go high, enabling the gate 136 and disabling the gate 134. If the remaining input switches associated with the primary code are actuated in the proper sequence, the gates 138 and 140;will be sequentially enabled and the preceding gate will be. disabled. Upon entry of the PRIMARY code 21335 each output of the register 74 will be a logic l. Likewise, if

the PRIMARY code has been entered and thelock'is the output of which is inverted by aninverter 148 and applied to the reset terminal of the flip-flop 58 in' the' clock geiierator 56. If after actuation of the first switch associat d with the first symbol in the'code, any of the pushbut ons Sl-S5 are'depressed'out of sequencef'a logic 0 appears at the output of the gate -144an'd is shifted t b'the outputof the flip-flop rash. that BITS is.

. a logied ,BIT4 will beia logic I as'a result of entry of the first symbol of the code or some number of se'quen-' tially correct symbols and consequently, the output of the gate 146 goes low'and the output of the inverter I 148 goes high to reset the flip-flop 58 causing its Q output to go low and the output of the gate 62 to go high.

Onthe following leading edge of the oscillator input the 0* .output of the flip-flop 60 goes lowand prevents any.

further'shifting in the register 74. With the clock input 3 to the register .74 inhibited,"no further. data may. be shifted in the register until'the ignition switch 88 is.

opened to reset the register and switch BIT4 low. From'theabove it will be apparent that, in the PR'I- MARY mode, BITS and BITI outputs of-the register 14;

' will both be a logic I only if the proper-PRIMARY- code is entered in the'correct sequence and that in the TURNOVER mode BITS andBIT3 outputs of the register 74 will both be a logic I only if the TURNOVER code is entered in the'proper sequence. These ouputs may be utilized to energize any appropriate electrical load device-to permit usage of the motorvehicle.

In the embodiment shown the ignition circuit is inhibited until the proper combination code, whether it be the PRIMARY or TURNOVER code, is entered. A relay 150 connected with lGN-l and to the collector of a transistor 152 controls relay contacts 156 in series between the ignition terminal of the ignition switch 88 and the ignition circuit. The emitter of transistor 152 is grounded and its base is connected through a resistor 158 to an inverter 154 which receives its input from NAND gate 160. One input to the NAND gate 160 is from BIT1* through NAND gates 162 and 164. The other input to the gate 162 is designated LOCKED while the other input to the gate 164 is BITS. The other input to the gate 160 is from a NAND gate 166, the inputs of which are BITS, BIT3, and TURNOVER. If all inputs to either of the gates 164 or 166 are high the output of the gate 160 will be high, the output of inverter 154 will be low rendering the transistor 152 nonconductive and deenergizing the relay 150 to connect the ignition circuit to the ignition switch 88. The output of the gate 160 provides the aforementioned UN- LOCKED input to the gate 124 of the mode flip-flop 116. UNLOCKED is also applied to the SET input of the flip-flop 60 to hold the STROBE output low once the ignition circuit has been unlocked.

An indicator circuit comprising a light emitting diode 168 is connected in series with a resistor 170 through the emitter-collector electrodes of a transistor 172. The base of the transistor 172 is connected through a resistor 174 and an inverter 176 to a NAND gate 178. Two of the inputs to the gate 178 are from the gates 164 and 166 while the other input is from the ignition switch 88 through a timing network comprising a diode 180, a capacitor 182, and a resistor 184.

As previously indicated, when the ignition switch 88 is opened the register 74 is reset and BITS is a logic 0 so that the outputs of the gates 164 and 166 are logic 1. Further, when the ignition switch 88 is opened, the capacitor 182 will begin to discharge through the resistor 184. For a time interval of, for example, seconds the third input to the gate 178 will be high. Since the other two inputs to the gate 178 are also high the transistor 172 is rendered conductive energizing the light emitting diode 168 forthe l5 second'interval to indicate that the system is locked. The diode 168 is also energized upon closure of the ignition switch 88 preparatory to entering the code to indicate the locked state of the ignition circuit.

As previously indicated, the output of the inverter 176 designated LOCKED, provides one input to the gate 162. When the system is operating in the TURN- OVER mode LOCKED will go low upon entry of the TURNOVER combination thusjdriving the output of the gate 162 high. Since BITS is 'high in either the TURNOVER or PRIMARY mode the output of the gate 164 is driven low. Consequently; when switching from the TURNOVER mode to the PRIMARY mode the resultant disabling of the gate 166 does not affect the gate 160 or the state of the ignition circuit since the gate 164 maintains the output of the gate 160 high.

Having thus described my invention what I claim is:

1. Combination lock circuitry for controlling energization of an electrical load device in response to entry of a predetermined combination code, said lock circuitry comprising:

a plurality of operator-actuable input switch means for entering the combination code;

I and to select the other of said codes in a multistage serial shift register having a data input,

a clock input, and an initializing input;

reset means connected to said initializing input for resetting the output of each stage of said register to a first of two logic levels;

clock generating means interconnecting said input switch means with said clock input for developing a clock pulse in response to actuation of any one of said input switch means;

a plurality of AND function performing gate means, the first of said AND gates being connected with the input switch means associated with the first symbol of said code, successive ones of said AND gates being connected with respective ones of said input switch means associated with successive symbols in said code;

means connecting the output of each of said AND gates with the data input of said register;

means connecting the output of certain stages of said register as inputs to certain of said AND gates to enable said first AND gate and disable the remaining AND gates when said register is reset and to sequentially enable said successive ones of said AND gates and sequentially disable the preceding AND gate upon actuation of the input switch means associated with the enabled gates;

means for inhibiting said clock means whenever the output of the first stage of said register is at said first logic level and the output of the second stage of said register is at the other logic level;

and means responsive to the output of the first and n'" (where n the number of symbols in the code) stage of said register for energizing said electrical load device when the outputs of the first and 11'' stage of said register are at said other logic level.

2. The circuitry defined in claim 1 further including select gate means connected between said switch means and said AND gates for selecting one or the other of two combination codes, said select gate means adapted to select one of said codes in response to simultaneous actuation of certain of said switch means response to entry of the first of said codes and simultaneous actuation of certain other of said switch means.

3. In a motor vehicle provided with a source of direct current and an ignition switch connected therewith:

electrical load means for preventing normal operation of said vehicle until energized;

electronic combination lock circuitry adapted to be connected with said source for energizing said load means in response to entry'of a PRIMARY or a TURNOVER combination code; i

said lock circuitry including a plurality of operator actuable input switch means for entering the combination codes; v

a multistage shift register having a plurality of flipflops, each flip-flop including a clock input, a data input, a reset input and an output, the output of each flip-flop being connected with the data input of the succeeding flip-flop;

means connecting said ignition switch to said reset inputs for resetting the output of each flip-flop of said register to a logic 0 level in response to opening of said ignition switch;

clock generator means interconnecting said input switch means with said clock inputs for developing a clock pulse in response to actuation of any one of said input switch means for transferring the logic.

sequence control means including a plurality of AND function performing gate means, OR function performing means having its inputs connected with the outputs of said AND gates and its output connected with the data input of the first flip-flop of said register;

mode flip-flop for developing a first output in response to simultaneous actuation of certain of said input switch means and for developing a second output in response to entry of said PRlMARY code and simultaneous actuation of certain others of said input switch means;

select gate means responsive to the outputs of said means connecting the output of certain flip-flops of said register as inputs to certain of said AND gates .to enable said first AND gate and disable the remaining AND gates when said register is reset and to sequentially enable said successive ones of said AND gates and sequentially disable the preceding AND gate upon actuation of the input switch means associated with the enabled gates;

means for inhibiting said clock generator means whenever the output of the first stage of said register is a logic 0 and the output of the second stage of said register is a logic 1;

and means responsive to the output of the first and n (where n the number of symbols in the code) flip-flop of said register for energizing said electrical load device when the output of the first and n'" flip-flop of said register are at a logic 1.

4. The circuitry defined in claim 3 further including indicator means;

time delay means for maintaining a logic level output for a predetermined interval of time subsequent to opening of said ignition switch;

additional AND function performing gate means responsive to the output of said time delay means and to resetting of said register for energizing saidindicator for said predetermined time interval to indicate to the operator that said electrical load means is deenergized. 

1. Combination lock circuitry for controlling energization of an electrical load device in response to entry of a predetermined combination code, said lock circuitry comprising: a plurality of operator-actuable input switch means for entering the combination code; a multistage serial shift register having a data input, a clock input, and an initializing input; reset means connected to said initializing input for resetting the output of each stage of said register to a first of two logic levels; clock generating means interconnecting said input switch means with said clock input for developing a clock pulse in response to actuation of any one of said input switch means; a plurality of AND function performing gate means, the first of said AND gates being connected with the input switch means associated with the first symbol of said code, successive ones of said AND gates being connected with respective ones of said input switch means associated with successive symbols in said code; means connecting the output of each of said AND gates with the data input of said register; means connecting the output of certain stages of said register as inputs to certain of said AND gates to enable said first AND gate and disable the remaining AND gates when said register is reset and to sequentially enable said successive ones of said AND gates and sequentially disable the preceding AND gate upon actuation of the input switch means associated with the enabled gates; means for inhibiting said clock means whenever the output of the first stage of said register is at said first logic level and the output of the second stage of said register is at the other logic level; and means responsive to the output of the first and nth (where n the number of symbols in the code) stage of said register for energizing said electrical load device when the outputs of the first and nth stage of said register are at said other logic level.
 2. The circuitry defined in claim 1 further including select gate means connected between said switch means and said AND gates for selecting one or the other of two combination codes, said select gate means adapted to select one of said codes in response to simultaneous actuation of certain of said switch means and to select the other of said codes in response to entry of the first of said codes and simultaneous actuation of certain other of said switch means.
 3. In a motor vehicle provided with a source of direct current and an ignition switch connected therewith: electrical load means for preventing normal operation of said vehicle until energized; electronic combination lock circuitry adapted to be connected with said source for energizing said load means in response to entry of a PRIMARY or a TURNOVER combination code; said lock circuitry including a plurality of operator actuable input switch means for entering the combination codes; a multistage shift register having a plurality of flip-flops, each flip-flop including a clock input, a data input, a reset input and an output, the output of each flip-flop being connected with the data input of the succeeding flip-flop; means connecting said ignition switch to said reset inputs for resetting the output of each flip-flop of said register to a logic 0 level in response to opening of said ignition switch; clock generator means interconnecting said input switch means with said clock inputs for developing a clock pulse in response to actuation of any one of said input switch means for transferring the logic level at the data input of each flip-flop to the output thereof; sequence control means including a plurality of AND function performing gate means, OR function performing means having its inputs connected with the outputs of said AND gates and its output connected with the data input of the first flip-flop of said register; a mode flip-flop for developing a first output in response to simultaneous actuation of certain of said input switch means and for developing a second output in response to entry of said PRIMARY code and simultaneous actuation of certain others of said input switch means; select gate means responsive to the outputs of said mode flip-flop for connecting one or the other of two groups of input switch means associated with said PRIMARY code or said TURNOVER code respectively to said AND gates, the first of said AND gate means being connected with the input switch means associated with the first symbol of said codes, successive ones of said AND gates being connected with respective ones of the input switch means associated with successive symbols in said codes; means connecting the output of certain flip-flops of said register as inputs to certain of said AND gates to enable said first AND gate and disable the remaining AND gates when said register is reset and to sequentially enable said successive ones of said AND gates and sequentially disable the preceding AND gate upon actuation of the input switch means associated with the enabled gates; means for inhibiting said clock generator means whenever the output of the first stage of said register is a logic 0 and the output of the second stage of said register is a logic 1; and means responsive to the output of the first and nth (where n the number of symbols in the code) flip-flop of said register for energizing said electrical load device when the output of the first and nth flip-flop of said register are at a logic
 1. 4. The circuitry defined in claim 3 further including indicator means; time delay means for maintaining a logic level output for a predetermined interval of time subsequent to opening of said ignition switch; additional AND function performing gate means responsive to the output of said time delay means and to resetting of said register for energizing said indicator for said predetermined time interval to indicate to the operator that said electrical load means is deenergized. 